Intel has developed AI tools to optimize SoC layouts in minutes, a significant reduction from 6 weeks. Cadence Live 2024 event in Santa Clara showcased advancements in chip design, including smaller die area and lower power consumption achieved by MediaTek using Cadence Cerebras digital design. Cadence integrated GenAI features into EDA chip design tools, driving improvements in productivity. The event highlighted Cadence's approach to the market and its product offerings, with a focus on AI-enhanced design tools driving productivity gains in chip design. Cadence announced new emulation and prototyping solutions, including the Paladium Z3 and Protium X3, with improved capacity, performance, and power efficiency. The event also featured the unveiling of new supercomputers aimed at accelerating chip and software development.
Just wrapped up another successful #CadenceLIVE! The latest trends in technology & innovation were on full display. Thank you to everyone who made it possible — our esteemed keynote speakers, Jensen Huang & @cristianoamon, & our sponsors, exhibitors, speakers & attendees. https://t.co/bO5Kc5wr6z
New Cadence supercomputers aim to speed creation of chips, software https://t.co/oYwgIPKsfZ https://t.co/9PaIL60q3R
Experience the future at the #CadenceLIVE Expo Hall! Cutting-edge exhibitors showcase trends in #AI, 3D-IC, cloud, automotive and more. Network with leaders, demo groundbreaking tech and discover solutions to give you a competitive advantage. https://t.co/qmqA7EKpjJ
.@Cadence believes in the future of automotive compute and will power @Tesla's next-genrration FSD and Dojo custom chips for automotive applications. #CadenceLive https://t.co/KwJBdkgBOG
The @Cadence Dynamic Duo III getting praise from @Nvidia, @SamsungDSGlobal, @AMD and @Arm. #CadenceLive https://t.co/4enBnrBBMN
.@Cadence announces the new Paladium Z3 emulation (48B Gates) a d Protium X3 for prototyping with matching 48B Gates. Huge improvements across the board in capacity and performance as well as power per gate. Protium @AMD FPGAs, @nvidia BlueField DPUs and Infiniband #CadenceLive https://t.co/5cLFQdnJIZ
.@Cadence shouting out customers like @MediaTek showing 5% smaller die area and 6% lower power using Cadence Cerebras digital design. #CadenceLive https://t.co/fHJfAGVacW
Attending @Cadence Live, I found this slide to be particularly impressive today . It’s a new world! https://t.co/b7A8DDLMCl
Impressive improvement numbers that @Cadence has achieved by integrating #GenAI powered features into several of their core EDA chip design tools. #CadenceLive https://t.co/heNPdPhF2r
The #AI enhanced design tools in @Cadence's tool suite are driving massive productivity improvements across many stages of the chip design process. #CadenceLIVE https://t.co/oGhc3d23rf
This is the @Cadence layer cake for Intelligent System Design. #CadenceLive https://t.co/KQ963YIWma
Nice visual overview of how @cadence is approaching the market highlighting its core categories and laying out where many of its specific product offerings fit. #CadenceLive https://t.co/YXo6xwTDJD
.@Cadence VP of Corporate Marketing KT Moore is on stage to kick off #CadenceLive https://t.co/FFAobabRT1
Starting the day off in Santa Clara at @Cadence LIVE 2024! https://t.co/RmvdxNvS4s
Intel uses in-house AI tools to optimize SoC layouts from 6 weeks, to just 'minutes' #DL #AI #ML #DeepLearning #ArtificialIntelligence #MachineLearning #ComputerVision #AutonomousVehicles #NeuroMorphic #Robotics https://t.co/ewebmBZ5ps